Embedded silicon germanium (eSiGe) is commonly used to introduce stress in the channel regions of, for example, PMOS devices to improve hole mobility and, therefore, device performance. The eSiGe is typically formed in a recess in the silicon substrate adjacent the channel region. However, during a typical SiGe deposition, the SiGe grows at a faster rate at bottom surfaces than sidewall surfaces of recesses. This results in an eSiGe layer of non-uniform thickness, particularly at the edges of the recess where the deposited SiGe tapers. The non-uniform thickness impairs efforts to engineer channel region strain and impacts the performance of the resulting device.
A need therefore exists for methodology enabling the adjustment of the relative growth rate of strain-inducing materials at the bottom and sidewall surfaces of recesses and the resulting devices.